Sumit Gupta's Neck of the Woods

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Sumit Gupta's Publications

Blogs, Press, and Recognition
Industry Articles and Presentations
Research Articles

Disclaimer -- The following publications and presentations are covered by copyright. The articles are provided here for reference and you may browse them in the same spirit as you may read a journal or a proceeding article in a public library. Retrieving, copying, distributing these files may violate copyright protection law. You may also need the permission of the publisher (IEEE/ACM) to re-print or distribute these articles.
(Former) Research Interests
Hardware and software synthesis and co-design, embedded system design, parallelizing compiler techniques, reconfigurable computing, low power design and power management of mobile devices.

Links to some of the papers I could find that cite my work
Google scholar's list of my papers with citations
Citations for my SPARK: A high-level synthesis ... paper as per Google Scholar

Press

Book(s)
  1. SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits,
    Sumit Gupta, R.K. Gupta, N.D. Dutt, A. Nicolau,
    Kluwer Academic Publishers. Buy now at Amazon.com
Book Chapters
  1. Parallelizing High Level Synthesis,
    G. Singh, Sumit Gupta, Sandeep Shukla, R. K. Gupta,
    The CRC Handbook of EDA for IC Design, Edited by Grant Martin, Luciano Lavagno, and Lou Scheffer
  2. ASIC Design,
    Sumit Gupta, R. K. Gupta,
    Chapter 64, The VLSI Handbook, Edited by Wai-Kai Chen, CRC Press and IEEE Press, 2000
  3. An Introductory Survey of Networked Embedded Systems,
    H. Patel, Sumit Gupta, Sandeep Shukla, R. K. Gupta,
    The Industrial Information Technology Handbook, edited by Richard Zurawski, CRC Press, 2003.
  4. Design Issues for Networked Embedded Systems,
    Sumit Gupta, H. Patel, Sandeep Shukla, R. K. Gupta,
    The Embedded Systems Handbook

Journal Papers

  1. Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis (pdf),
    S. Gupta, R.K. Gupta, N.D. Dutt, A. Nicolau,
    ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 9, Issue 4, October 2004
  2. Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis (pdf)
    S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta, A. Nicolau,
    IEEE Transactions on Computer-Aided Design, Vol 23, No. 2, February 2004.
  3. Dynamically Increasing the Scope of Code Motions during the High-Level Synthesis of Digital Circuits, (pdf)
    S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Invited Paper in Special Issue of IEE Proceedings: Computers and Digital Technique: Best of DATE 2003, Vol 150(5), September 2003.

Conference Papers

    Coarse-Grain Reconfigurable Computing

  1. Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures, (pdf)
    N. Bansal, S. Gupta, N.D. Dutt, A. Nicolau, R.K. Gupta,
    Design, Automation and Test in Europe, Feb. 2004
  2. Analysis of the Performance of Coarse-Grain Reconfigurable Architectures with Different Processing Element Configurations(pdf),
    N. Bansal, S. Gupta, N.D. Dutt, A. Nicolau,
    Workshop on Application Specific Processors (WASP), held in conjunction with the 36th International Symposium on Microarchitecture (MICRO), 2003.
  3. Low Power Design and Power Management of Mobile Devices

  4. Proxy-based Task Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices
    Arun Kejariwal S. Gupta, N.D. Dutt, A. Nicolau, R.K. Gupta,
    Design Automation Conference (DAC), June 2004
  5. System Level Design and Interface Synthesis

  6. Hardware and Interface Synthesis of FPGA Blocks using Parallelizing Code Transformations, (pdf)
    S. Gupta, M. Luthra, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Invited talk at the special session on Synthesis For Programmable Systems at the International Conference on Parallel and Distributed Computing and Systems, November 2003
  7. Interface Synthesis using Memory Mapping for an FPGA Platform, (pdf)
    M. Luthra, S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau,
    International Conference on Computer Design, October 2003
  8. Parallelizing High-Level Synthesis

  9. Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow, (pdf)
    S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Design, Automation and Test in Europe, Feb. 2004
  10. Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs, (pdf)
    S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Design, Automation and Test in Europe, March 2003
  11. SPARK : A High-Level Synthesis Framework For Applying Parallelizing Compiler Transformations (pdf)
    S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau,
    International Conference on VLSI Design, January 2003
    Best Paper Award
  12. Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis (pdf)
    S. Gupta, M. Reshadi, N. Savoiu, N.D. Dutt, R.K. Gupta, A. Nicolau,
    International Symposium on System Synthesis, October 2002
  13. Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks (pdf)
    S. Gupta, T. Kam, M. Kishinevsky, S. Rotem, N. Savoiu, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Design Automation Conference, June 2002
  14. Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis (pdf)
    S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta, A. Nicolau,
    International Symposium on System Synthesis, October 2001
  15. Speculation Techniques for High Level synthesis of Control Intensive Designs (pdf)
    S. Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Design Automation Conference, June 2001
  16. Synthesis of Testable RTL Designs using Adaptive Simulated Annealing Algorithm (pdf)
    C.P. Ravikumar, S. Gupta, A. Jajoo,
    International Conference on VLSI Design, Jan '98
    Best Student Paper Award
  17. High-Level Compiler Transformations

  18. Analysis of High-level Address Code Transformations for Programmable Processors (pdf)
    S. Gupta, M. Miranda, F. Catthoor, R. K. Gupta,
    Design, Automation and Test in Europe (DATE), Paris, March 2000

Thesis

  • Coordinated Coarse-Grain and Fine-Grain Optimizations for High-Level Synthesis,
    Sumit Gupta,
    School of Information and Computer Science, University of California, Irvine, June 2003.

Technical Reports

  1. Energy Efficient Communication for Reliability and Quality Aware Sensor Networks, (pdf)
    C. Pereira, S. Gupta, K. Niyogi, I. Lazaridis, S. Mehrotra R. Gupta. CECS Technical Report #03-15, University of California, Irvine, April, 2003
  2. Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis
    S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Technical Report #CECS-TR-02-35, Center for Embedded Computer Systems, University of California, Irvine, December 2002
  3. Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis
    S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Technical Report #CECS-TR-02-29, Center for Embedded Computer Systems, University of California, Irvine, October 2002
  4. Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis ,
    S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Technical Report #01-25, Dept. of Information and Computer Science, Univ. of California, Irvine, June 2001
  5. Speculation Techniques for High Level synthesis of Control Intensive Designs (pdf)
    S. Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta, A. Nicolau,
    Tech. Rep. #00-40, Dept. of Information and Computer Science, Univ. of California, Irvine, Dec. 2000
  6. Analysis of High-level Address Code Transformations for Programmable Processors (pdf),
    S. Gupta, M. Miranda, F. Catthoor, R. K. Gupta,
    Tech. Rep. #00-04, Dept. of Information and Computer Science, Univ. of California, Irvine, Apr. 2000
  7. Software Synthesis using Timed Decision Tables (pdf),
    S. Gupta, R. K. Gupta,
    Tech. Rep. #99-01, Dept. of Information and Computer Science, Univ. of California, Irvine, Jan. 1999
    ( associated software release of Topts)
  8. Distributed Adaptive Simulated Annealing for Synthesis Design Space Exploration (pdf),
    S. Gupta, L. Bic,
    Tech. Rep. #99-05, Dept. of Information and Computer Science, Univ. of California, Irvine, Jan. 1999
  9. Advanced Code-hoisting and Induction-Variable Analysis Techniques for High-level Address Optimisation,
    S. Gupta, M. Miranda, F. Catthoor,
    Internal Technical Report, VLSI Systems Design Methodology Division, IMEC vzw, September, 1998

B.Tech. Thesis

  • An Intelligent Tool for Automatic Synthesis of Testable Data Paths,
    S. Gupta, B.Tech. Thesis, Dept. of Electrical Engg., IIT Delhi, May 1995

Invited Talks and Presentations

  • Special session on Synthesis For Programmable Systems at the International Conference on Parallel and Distributed Computing and Systems, November 2003.
  • University of California, Berkeley: joint talk at the Electronics Design Seminar Series and the Center for Hybrid and Embedded Software Systems (CHESS) Weekly Workshops, October 2003.
  • Xilinx Research Labs, San Jose, May 2003.
  • University of California, Riverside, Computer Science Department, April 2003.
  • NEC Research Labs, Princeton, February 2003.
  • Semiconductor Research Corporation (SRC) review committee, 2001.
  • Presentation to members of Strategic CAD Labs, Intel, 2001.
  • University Booth at Design Automation Conference, 2001: ``The SPARK High Level Synthesis System''.
  • Ph.D. Forum at Design Automation Conference, 2000: ``Generalized Code Motions for Improved Resource Sharing in High-level Synthesis''
  • University Booth at Design Automation Conference, 1998: ``Pre-synthesis Optimizations of HDL Code using a behavioral table format known as Timed Decision Tables''.

Posters and other Misc. Presentations

  • DAC University Booth: The SPARK High Level Synthesis System, Design Automation Conference, June, 2001
  • Poster at the DAC Phd Forum: Generalized Code Motions for improved Resource Sharing in High-level Synthesis, Design Automation Conference, 2000
  • University Booth: Pre-synthesis Optimizations of HDL Code using a behavioral table format known as Timed Decision Tables, Design Automation Conference, 1998

Service, misc.


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