Sumit Gupta's Neck of the Woods


Sumit Gupta's Neck of the Woods

This page is super old and not maintained. Visit my LinkedIn profile for the latest.

Currently at NVIDIA: Tesla GPU Computing (CUDA) Group Sumit Gupta's Photo
Doing General Manager, Tesla GPU Accelerated Computing Business Unit
Email sumitg at
Education Phd, CS (Embedded Systems), UC Irvine, 2003
B.Tech., EE, IIT Delhi, 1995
Resume SumitGuptaResume.pdf


The gamut of my work experience ranges from product management, business management and product marketing to ASIC design to writing parallelizing compilers to EDA tools to FPGAs.

NVIDIA Logo I currently manage the Tesla GPU Accelerated Computing business unit at NVIDIA. We promote the use of GPUs as very high performance accelerators that fit into standard x86 CPU based servers, workstations, and PCs. GPUs are massively parallel computing processors that accelerate applications that range from big data analytics to seismic processing in oil and gas, to sequence searches and alignment in bio-informatics, and risk analysis and options pricing in financial services.

NVIDIA's GPUs have evolved over the years to become massively parallel with 1000s of processor cores. This architecture is called the CUDA parallel computing architecture and enables GPU computing (also called GPGPU). The same floating point performance that is useful for graphics is also useful for scientific, technical, biological, imaging, and financial computing. The reason GPUs have become so popular as accelerators is that they are programmable using C, C++, Fortran using simple extensions or keywords, known as the CUDA extensions.

Tensilica Logo Prior to this, I was product manager at Tensilica responsible for the Xtensa and Diamond processor IP cores. I did both inbound product management (product definition, roadmap), and outbound product marketing (launches, sales assistance, collateral, sales tools).

Tallwood Logo Before this, I was an Entrepreneur-in-Residence at Tallwood Venture Capital, where I analyzed technological innovations and market forces in the reconfigurable, FPGA, and programmable spaces. I did market research and due diligence on business plans.

IBM Logo I worked for a few years in India after graduating from IIT Delhi. My first job was as a Software Engineer at IBM Global Services, in Bangalore India.

S3 Logo I then moved to a startup (as employee 5) called S3 India, where I worked on ASIC design as part of a media processor design team.

I also did some part-time research with Prof Sriram Vajapeyam at SERC, Indian Institute of Science, Bangalore during the 1996-1997 time frame.

IMEC During the summer of 1998, I interned with the VLSI Systems Design and Methodologies group at IMEC in Leuven, Belgium. During the same summer, I also travelled through several parts of Europe (needless to say that was fun !).

Intel Logo In the summer of 2001, I interned with the Strategic CAD Labs at Intel, in Portland, Oregon. Oregon is a beautiful state with lots of outdoor activities and sights.

During my technical days, I wrote large software tools -- the SPARK synthesis tool is 100K+ lines of C++ code -- and large hardware descriptions -- specifically, the RTL description of the data path of the media processor and the custom design of a complex SIMD 32-bit multiplier.

Life as I remember it started in Kuwait (although I was born in Bhilai, Madhya Pradesh, India). I studied at the Indian School, Kuwait till the Iraqi invasion of Kuwait, after which I spent my "refugee" days in Delhi. I completed my high school at Mother's International School, Delhi in 1991.

IIT Delhi Logo IIT Delhi Photo I then went on to pick up a B.Tech in Electrical Engineering in 1995 from IIT Delhi (Indian Institute of Technology Delhi). (You can register yourself at this site, if you are an IIT Delhi Alumnus and at the IIT Delhi Alumni Association web page.)

I received a Phd from the School of Information and Computer science at UC, Irvine. For my Ph.D., I worked on the crossroads of compiler technology and embedded system design and design automation. I (with a little/lot of help from my friends) built a C-based parallelizing high-level synthesis framework called SPARK. The novel parallelizing high-level synthesis methodology that we developed for SPARK presents a leap forward in improving the quality of results for high-level synthesis. My Ph.D. advisor was Prof Rajesh Gupta, who heads the Microlectronic Embedded System Lab at the Computer Science and Engineering Dept, at the University of California at San Diego.
Next, I did Post-doctoral research at the Center for Embedded Computer Systems on reconfigurable computing and system-level design and synthesis at UC San Diego & UC Irvine.

On the lighter side, I enjoy outdoor sports and am (was) into rock climbing, tennis, hiking. My last passion (before I became a family man) was Aikido with Sensei Haruo Matsuoka. I have also learnt some Wushu from Sifu Vadim Zukhov.

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